Patterned wiring layers allow the transmission of electronic signals between different portions of a semiconductor device. Multiple patterned wiring layers can be provided on a semiconductor device wherein each wiring layer is separated by an insulating layer. Portions of upper and lower wiring layers can thus be connected by contact plugs through the insulating layer therebetween.
FIGS. 1A to 1D are cross-sectional views illustrating steps of a method for forming a contact plug according to the prior art. As shown in FIG. 1D, the completed structure includes a semiconductor substrate 1, an interlayer insulating layer 3, a patterned wiring layer 5, an insulating layer 7, a contact hole 8, a barrier layer 9, and a conductive layer 11. As shown in FIG. 1A, a layer of a metal such as aluminum is deposited on the insulating layer 3 and patterned to provide the patterned wiring layer 5 on the insulating layer 3 opposite the substrate 1. The insulating layer 7 is then deposited on the patterned wiring layer 5 and the insulating layer 3. As shown, the insulating layer 7 may have steps therein due to the patterned wiring layer 5.
The insulating layer 7 is then planarized using a chemical-mechanical polishing (CMP) step. The chemical-mechanical polishing step is performed for a predetermined period of time so that the planarized insulating layer 7 of FIG. 1B has a desired thickness. A cleaning step such as a spin scrub is then performed to remove particles generated during the polishing step.
As shown in FIG. 1C, the planarized insulating layer 7 is selectively etched to form contact holes 8 therein exposing surface portions of the patterned wiring layer 5. This selective etch can be performed using photolithographic techniques. A titanium (Ti) layer and a titanium nitride (TiN) layer are sequentially deposited on the insulating layer 7 and in the contact hole 8 to provide the barrier layer 9 having a titanium nitride/titanium structure. Tungsten (W) is then deposited on the barrier layer 9 thereby providing the conductive layer 11.
As shown in FIG. 1D, the conductive layer 11 and the barrier layer 9 are polished back using a chemical-mechanical polishing step until the planarized insulating layer 7 is exposed. In particular, a polishing agent is used wherein the polishing rate of the conductive layer 11 and the barrier layer 9 is roughly the same as the polishing rate of the insulating layer 7. Accordingly, the contact plug 11 is provided including the remaining portions of the conductive layer 11 and the barrier layer 9 in the contact hole 8. Because the planarized insulating layer 7 may not provide an effective polishing stop, it may be difficult to accurately end the polishing step. In addition, a cleaning step can be used to remove particles generated during the polishing step.
According to the method discussed above, the polishing step may need to be performed in a chemical-mechanical polishing (CMP) system, and the cleaning step may need to be performed in a separate cleaning system thereby complicating the method.